1. Field of the Invention
The invention relates to methods and tools for device placement in custom designed VLSI circuits, and especially to schematic driven placement method for custom VLSI circuit design, thereby enabling fast prototyping of layout with placed VLSI circuits for area and size estimation and routing.
2. Background Art
Generally in custom VLSI circuit design the placement of circuits in the layout is done after the schematic is completely done. Circuit placements in custom design are done either graphically or through a unique placement routine for each design, i.e., a Cadence Skillcode based routine. If the circuits placement is done graphically, it usually takes designer some effort to make the placement ground rule correct. If there is any update on either the device size or topology in the schematic, the placement in the layout has to be redone manually. Area, size and form factor of the design are estimated based on the floorplan, total device width in the schematic, and projected wiring tracks required to route the design. Skill code driven placement usually requires customized functions and hard coded instance names, thus demanding distinct coding efforts for each macro placed. This provides limited scalability, and extensibility, and makes entry of engineering changes difficult.